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Archive-name: pc-hardware-faq/chiplist/part3
Last-modified: 1998/06/14
Version: 9.9.5
2.32 Intel i80486 CPU
Intel i80386 CPU upward instruction compatible.
Extra instructions.
8 kbyte unified cache: write-through, 4-way set-associative, 128 sets,
16 bytes per cache line, 4 write buffers,
only invalidation of a complete cache line,
96 % hit rate.
32 bit internal data bus.
32 bit external data bus.
32 bit address bus.
Execution unit:
5-stage pipeline,
barrel shifter,
branch taken / not taken prediction (BTB: Branch Target Buffer).
Burst mode memory access: first access: 2 clock cycles,
every next access: 1 clock cycle.
2.32.1 Intel i80486DX P4 CPU
Build-in FPU (Floating Point Unit).
April 1989.
20 MHz: CMOS.
25 MHz: 2600 mW, CHMOS IV, iCOMP 122, no longer available.
33 MHz: 3500 mW, CHMOS IV.
50 MHz: June 1991, 3875 mW, CHMOS V.
Upgrading: Intel i80486DX2 CPU (ODPR), Intel OverDrive CPU (ODP:
Intel i80486DX2 CPU), Intel i80486DX4 CPU (ODPR),
Intel OverDrive CPU (ODP: Intel i80486DX4 CPU), Intel OverDrive CPU
(ODPR: Intel Pentium CPU with Intel i80486DX CPU bus interface),
Intel OverDrive CPU (ODP: Intel Pentium CPU).
Package: 168 pin PGA (Pin Grid Array).
1.185E6 transistors.
Die size: 165 mm2.
From June 1993 (Intel i80486DX-S CPU):
SL Enhanced.
33 MHz: iCOMP 166.
50 MHz: iCOMP 249.
CPUID: family = 0x4, model = 0x1.
From June 1993:
SL Enhanced.
Low power: 3.3 V.
33 MHz.
No longer available from second quarter 1995.
ID (25 - 33 MHz, CMOS IV):
step level A0, A1: DH = 0x04 (family ID), DL = 0x00 (model ID, revision),
step level B2-B6: DH= 0x04 (family ID), DL = 0x01 (model ID, revision),
step level C0: DH = 0x04 (family ID), DL = 0x02 (model ID, revision),
step level C1: DH = 0x04 (family ID), DL = 0x03 (model ID, revision),
step level D0: DH = 0x04 (family ID), DL = 0x04 (model ID, revision).
ID (50 MHz, CMOS V):
step level cA2, cA3: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level cB0, cB1: DH = 0x04 (family ID), DL = 0x11 (model ID, revision),
step level cC0: DH = 0x04 (family ID), DL = 0x13 (model ID, revision),
step level aA0, aA1 (SL Enhanced): DH = 0x04 (family ID), DL = 0x14
(model ID, revision),
step level aB0 (SL Enhanced): DH = 0x04 (family ID), DL = 0x15 (model ID,
revision).
2.32.2 Intel i80486SL CPU
Intel i80486DX CPU with extra features:
DRAM controller,
ISA (Industry Standard Architecture) controller,
local PI-bus controller (Peripheral Interconnect),
power management: SMM (System Management Mode).
Static core.
25 Mhz.
33 MHz.
Not Intel i80486DX CPU pin compatible.
196 pin PQFP (Plastic Quad Flat Package).
Technology: CMOS.
From June 1993 replaced by Intel i80486DX-S CPU.
ID: step level A: DH = 0x04 (family ID), DL = 0x40 (model ID, revision).
2.32.3 Intel i80486DXL CPU
Intel i80486DX CPU with extra features: SMM (System Management Mode),
stop clock,
power saving features.
Static core.
Technology: CMOS.
2.32.4 Intel i80486SX P23 CPU
No build-in FPU (Floating Point Unit):
Intel i80486DX CPU die with FPU disabled,
currently FPU not implemented (resulting in a smaller chip, plastic package).
One extra pin assigned to allow an Intel i80487SX NPX to disable this CPU.
Not Intel i80486DX CPU upward pin compatible.
Package: 168 pin PGA (Pin Grid Array).
April 1991.
16 MHz: 1991, no longer available.
20 MHz: 1991, iCOMP 78, no longer available.
25 MHz: 1991, iCOMP 100 (per definition).
33 MHz: 1991.
Upgrading: Intel i80486DX CPU (ODPR: Intel i80486DX CPU with
Intel i80486SX CPU pin layout), Intel i80486DX2 CPU (ODPR:
Intel i80486DX2 CPU with Intel i80486SX CPU pin layout),
Intel OverDrive CPU (ODP: Intel i80486DX2 CPU), Intel i80486DX4 CPU
(ODPR: Intel i80486DX4 CPU with Intel i80486SX CPU pin layout),
Intel OverDrive CPU (ODP: Intel i80486DX4 CPU), Intel OverDrive CPU
(ODPR: Intel Pentium CPU with Intel i80486SX CPU bus interface),
Intel OverDrive CPU (ODP: Intel Pentium CPU).
Package: 168 pin PGA (Pin Grid Array),
208 pin PQFP (Plastic Quad Flat Package).
Technology: CMOS.
0.9E6 transistors.
From June 1993 (Intel i80486SX-S CPU):
SL Enhanced.
25 MHz: iCOMP 100 (by define).
33 MHz: iCOMP 136.
CPUID: family = 0x4, model = 0x2.
From June 1993:
SL Enhanced.
Low Power: 3.3 V.
25 MHz.
33 MHz.
ID: step level A0: DH = 0x04 (family ID), DL = 0x20 (model ID, revision),
step level B0: DH = 0x04 (family ID), DL = 0x22 (model ID, revision),
step level cA0: DH = 0x04 (family ID), DL = 0x27 (model ID, revision),
step level cB0: DH = 0x04 (family ID), DL = 0x28 (model ID, revision),
step level D: DH = 0x04 (family ID), DL = 0x23 (model ID, revision),
step level E: DH = 0x04 (family ID), DL = 0x2A (model ID, revision),
step level gAx: DH = 0x04 (family ID), DL = 0x24 (model ID, revision),
step level aA0, aA1: DH = 0x04 (family ID), DL = 0x2A (model ID,
revision),
step level aB0, aC0: DH = 0x04 (family ID), DL = 0x2B (model ID,
revision).
2.32.5 Intel i80486SXL CPU
Intel i80486SX CPU with extra features: SMM (System Management Mode),
stop clock,
power saving features.
static core.
Technology: CMOS.
2.32.6 Intel i80486DX2 P24 CPU
Clock doubled version of the Intel i80486DX CPU.
Intel i80486DX CPU pin compatible.
March 1992.
20/40 MHz.
25/50 MHz: 4000 mW.
33/66 MHz: 4875 mW.
G4C, G4S.
Technology: CMOS.
1.2E6 transistors.
Die size: 230 mm2.
From June 1993 (Intel i80486DX2-S CPU):
SL Enhanced.
20/40 MHz: SQFP (Shrink Quad Flat Package).
25/50 MHz: iCOMP 231.
33/66 MHz: iCOMP 297.
CPUID: family = 0x4, model = 0x3.
From Nov 1993:
SL Enhanced.
Low power: 3.3 V.
20/40 MHz.
25/50 MHz.
From October 1994 (P24D) (not marketed, P24CT OverDrive Processor Pretest Kit
for Intel Verification Program (OEM)):
Write-back cache.
Upward pin compatible.
Performance increase: 15 %.
25/50 MHz.
33/66 MHz.
No longer available from fourth quarter 1995.
ID: step level A0-A2: DH = 0x04 (family ID), DL = 0x32 (model ID, revision),
step level B1: DH = 0x04 (family ID), DL = 0x33 (model ID, revision),
step level aA0, aA1 (SL Enhanced): DH = 0x04 (family ID), DL = 0x34
(model ID, revision),
step level aB0, aC0 (SL Enhanced): DH = 0x04 (family ID), DL = 0x35
(model ID, revision),
step level A (write-back): DH = 0x04 (family ID), DL = 0x36 (model ID,
write-through), DL = 0x7X (model ID,
write-back).
2.32.7 Intel i80486DX4 P24C CPU
Clock tripled version of the Intel i80486DX CPU.
Selection of doubling/tripling by a pin on the chip (CLKMUL: 0, 1). Connecting
this pin with the BREQ pin makes the core running at 2.5 times the external
speed (not implemented yet).
Intel i80486DX CPU upward pin compatible.
5 V external, 3.3 V internal: if the motherboard does not provide the 3.3 V
power to the CPU, the CPU can be installed using
a special socket wired to the 3.3 V output of
your PSU (Power Supply Unit); in either case
another PSU providing the 3.3 V is needed.
3.3 V.
16 kbyte cache.
25/75 MHz max (A80486DX475): 3.3 V, March 1994, iCOMP 319.
33/100 MHz max (A80486DX4100): 51 SPECint92, 27 SPECfp92, 3.3 V, March 1994,
iCOMP 435.
Production cancelled for a few months from September 1994 in favor of
Intel Pentium CPUs.
Power consumption: 4 W typical.
SL Enhanced Intel i80486DX CPU pin compatible.
Package: 168 pin PGA (Pin Grid Array).
Extra integer multiplier: 5 cycle 16 x 16 multiply.
Package: 168 pin PGA (Pin Grid Array),
208 pin SQFP (Shrink Quad Flat Package).
Technology: 4-layer metal, 0.6 micron biCMOS/CHMOS.
1.6E6 transistors.
Die size: 87 mm2.
ID: step level A: DH = 0x04 (family ID), DL = 0x8X (model ID, revision).
CPUID: step level A: family = 0x4, model = 0x8.
From October 1994 (Intel i80486DX4WB CPU): write-back cache.
Code: &EW.
Intel i80486DX4 P54LM CPU: notebooks,
2.5 - 2.9 V,
90 MHz,
100 MHz.
2.32.8 Intel i80486SX2 CPU
Clock doubled version of the Intel i80486SX CPU.
SL Enhanced.
25/50 MHz: March 1994, iCOMP 180.
33/66 MHz.
ID: step level aC0: DH = 0x04 (family ID), DL = 0x5B (model ID, revision).
2.33 AMD Am486 CPU
Originally same core and microcode as Intel i80486 CPUs; currently an own
implementation. In between there were CPUs with recompiled 486 microcode.
Intel i80486 CPU instruction compatible.
All current Enhanced AMD processors support the CPUID instruction.
2.33.1 AMD Am486DX CPU
Intel i80486DX CPU instruction/pin compatible.
Cache: 8 kbyte, write-through.
April 1993.
25 MHz.
33 MHz: 8-33 MHz, 1993.
40 MHz: 8-40 MHz, 1993.
Technology: CMOS.
1E6 transitors.
Die size: 89 mm2.
ID: DH = 0x04 (family ID), DL = 0x1X (model ID, revision),
DH = 0x04 (family ID), DL = 0x12 (model ID, revision).
2.33.2 AMD Am486DXL CPU
Low power version of the AMD Am486DX CPU.
October 1993.
40 MHz.
Technology: CMOS.
ID: DH = 0x04 (model ID), DL = 0x12 (model ID, revision).
2.33.3 AMD Am486DXLV CPU
Low power (SMM: System Management Mode), low voltage (3.0 V) version of the
AMD Am486DX CPU.
Static core.
October 1993.
33 MHz: 0-33 MHz, 1993.
Technology: CMOS.
ID: DH = 0x04 (model ID), DL = 0x12 (model ID, revision).
2.33.4 AMD Am486DX2 CPU
Clock doubled version of the AMD Am486DX CPU.
April / October 1993.
From November 1994: 3.3 V.
25/50 MHz: 1993.
33/66 MHz: heatsink required.
40/80 MHz: September 1994, heatsink required.
50/100 MHz.
Some 3.3 V, 66, 80 MHz items are DX4 parts that failed Q.C. at 100 MHz
(Malaysia, fab number 25253).
Technology: CMOS.
ID: DH = 0x04 (family ID), DL = 0x3X (model ID, revision).
AMD Enhanced Am486DX2 CPU:
cache: write-through / write-back,
33/66 MHz,
40/80 MHz,
50/100 MHz,
DX register & CPUID: 0x43X (write-through cache),
0x47X (write-back cache).
2.33.5 AMD Am486DXL2 CPU
Clock doubled version of the AMD Am486DXL CPU.
Low power (SMM: System Management Mode).
AMD core/microcode.
33/66 MHz.
40/80 MHz.
Technology: CMOS.
ID: DH = 0x04 (family ID), DL = 0x32 (model ID, revision).
2.33.6 AMD Am486DX4 CPU
Clock tripled version of the AMD Am486DX CPU.
Intel i80486DX4 CPU pin compatible.
Selection of doubling/tripling by a pin on the chip.
8 kbyte cache: write-through.
33/100 MHz: 3.3 V, September 1994, heatsink + fan required.
40/120 MHz: 3.3 V.
Technology: 3-layer metal, 0.5 micron CMOS.
ID: DH = 0x04 (family ID), DL = 0x3X (model ID, revision),
DH = 0x04 (family ID), DL = 0x32 (model ID, revision).
AMD Am80486DX4-xxxNT8T CPU.
AMD Am80486DX4-xxxNV8T CPU.
Enhanced AMD Am486DX4 CPU (AMD Am80486DX4-xxxSV8B CPU):
SL Enhanced,
write-through / write-back cache,
3.3 V,
25/75 MHz,
33/100 MHz,
40/120 MHz,
package: 169 pin PGA (Pin Grid Array),
208 pin SQFP,
AMD Enhanced Am486DX4 CPU (write-through cache): DX register & CPUID: 0x48x,
AMD Enhanced Am486DX4W CPU (write-back cache): DX register & CPUID: 0x49x,
label: A 80486DX4-100 SV8B:
S: SMM (System Management Mode),
N: standard,
V: low power,
_: standard,
8: 8 kbyte cache,
B: write-back cache,
T: write-through cache.
2.33.7 AMD Am486SX CPU
Intel i80486SX CPU instruction/pin compatible.
AMD microcode.
July 1993.
33 MHz: 1993.
40 MHz: 1993.
Technology: CMOS.
2.33.8 AMD Am486SXLV CPU
Low power (SMM: System Management Mode), low voltage (3.0 V) version of the
AMD Am486SX CPU.
Static core.
AMD microcode.
July 1993.
33 MHz.
Technology: CMOS.
2.33.9 AMD Am486SX2 CPU
Clock doubled version of the AMD Am486SX CPU.
25/50 MHz: February 1994.
33/66 MHz: April 1994.
2.33.10 AMD Am486SE CPU
Embedded static version of the AMD Am486SX CPU.
25 MHz: 1995.
33 MHz: 1995.
Package: CGM168.
AMD Embedded Processors E86 Family.
2.33.11 AMD Am486DX4 SE CPU
Embedded static version of the AMD Am486DX4 CPU.
40/120 MHz.
AMD Embedded Processors E86 Family.
2.33.12 AMD Am5x86 X5 CPU
Clock quadrupled Enhanced 486.
SL Enhanced Intel i80486DX2 CPU (P24D) pin compatible.
16 kbyte cache: write-through / write-back.
33/133 MHz (AMD Am5x86-P75, AMD 486X5-133): November 1995.
40/160 MHz.
3.3 V, 3.45 V.
Technology: 35 micron CMOS.
Die size: 43 mm2.
DX register & CPUID: 0x04EX (write-through),
0x04FX (write-back).
Label: Amd 5x86-P75 ADW:
A: PGA (Pin Grid Array),
S: SQFP,
D: 3.45 +- 0.15 V,
F: 3.3 +- 0.15 V,
W: case temperature 55 C,
Y: 75 C,
Z: 85 C.
2.34 IBM 80486 CPU
Intel i80486 CPU instruction compatible.
2.34.1 IBM 80486DX CPU
Intel i80486DX CPU instruction/pin compatible.
8 kbyte cache.
Technology: CMOS.
2.34.2 IBM 80486SX CPU
Intel i80486SX CPU instruction/pin compatible.
16 kbyte cache.
Technology: CMOS.
2.34.3 IBM 80486BLDX2 CPU (Blue Lightning)
33/66 MHz: Cyrix FasCache Cx486DX2-V-66 CPU.
40/80 MHz: Cyrix FasCache Cx486DX2-V-80 CPU.
ID: DH = 0xA4 (family ID), DL = 0x80 (model ID, revision).
2.35 IBM 5x86C CPU
Cyrix 5x86 CPU.
25/75 MHz.
IBM265x86-3V3100GB: 33/100 MHz, package: PGA (Pin Grid Array).
IBM265x86-3V3100QB: 33/100 MHz, package: PQFP (Plastic Quad Flat Package).
2.36 Cyrix Cx486 CPU
2.36.1 Cyrix FasCache Cx486D CPU
Intel i80486 CPU instruction compatible, no build-in FPU (Floating Point
Unit).
Can piggy-back a Cyrix Cx487S NPX.
2 kbyte cache: write-back.
Intel i80486SX CPU upward pin compatible.
On-chip ventilator.
40 MHz: 1993.
Technology: CMOS.
Cyrix M5 CPU.
ID: DH = 0x00 (family ID), DL = 0x05 (model ID).
2.36.2 Cyrix FasCache Cx486S CPU
Intel i80486 CPU instruction compatible, no build-in FPU (Floating Point
Unit).
Low Power: SMM (System Management Mode).
Static core.
2 kbyte cache: write-back.
Intel i80486SX CPU upward pin compatible.
May 1993.
33 MHz.
40 MHz: 1993.
50 MHz.
Technology: CMOS.
Cyrix M5 CPU.
ID: DH = 0x00 (family ID), DL = 0x05 (model ID).
DIR0 register: 0x10.
2.36.3 Cyrix FasCache Cx486S/e CPU
Low power (SMM: System Management Mode) version of the
Cyrix FasCache Cx486S CPU.
Static core.
DIR0 register: 0x12.
2.36.4 Cyrix FasCache Cx486S-V CPU
Low voltage (3.3 V) version of the Cyrix FasCache Cx486S CPU.
May 1993.
25 MHz.
33 MHz.
Technology: CMOS.
DIR0 register: 0x10.
2.36.5 Cyrix FasCache Cx486S2 CPU
Clock doubled version of the Cyrix FasCache Cx486S CPU.
October 1993.
20/40 MHz.
25/50 MHz.
Technology: CMOS.
DIR0 register: 0x11.
2.36.6 Cyrix FasCache Cx486S2/e CPU
Low power (SMM: System Management Mode) version of the
Cyrix FasCache Cx486S2 CPU.
Static core.
DIR0 register: 0x13.
2.36.7 Cyrix FasCache Cx486S2-V CPU
Low voltage (3.3 V) version of the Cyrix FasCache Cx486S2 CPU.
October 1993.
20/40 MHz.
25/50 MHz.
Technology: CMOS.
DIR0 register: 0x11.
Cyrix FasCache Cx486DX/Cx486DX2 CPU FP bug: when a register load instruction
is followed by an instruction that clears the FP status register (FCLEX), and
the memory location being referenced is not in the CPU's internal cache, the
external memory bus cycle is aborted by the FCLEX instruction and the register
is not loaded properly.
Since this code sequence is very unlikely to occur in any software, the bug
will probably not be fixed at all.
2.36.8 Cyrix FasCache Cx486DX CPU
Intel i80486DX instruction compatible, FPU (Floating Point Unit).
Low Power: SMM (System Management Mode).
Static core.
8 kbyte cache: write-through / write-back.
Intel i80486DX CPU upward pin compatible.
September 1993.
33 MHz: 1993.
40 MHz: 1993.
50 MHz.
Technology: CMOS.
1.1E6 transistors.
Die size: 196 mm2.
Cyrix M6 CPU.
ID: DH = 0x00 (family ID), DL = 0x06 (model ID).
DIR0 register: 0x1A.
2.36.9 Cyrix FasCache Cx486DX-V33 CPU
Low voltage (3.3 V) version of the Cyrix FasCache Cx486DX CPU.
September 1993.
25 MHz.
33 MHz.
Technology: CMOS.
ID: DH = 0x00 (family ID), DL = 0x06 (model ID).
DIR0 register: 0x1A.
2.36.10 Cyrix FasCache Cx486DX2 CPU
Clock doubled Cyrix FasCache Cx486DX CPU.
September 1993.
20/40 MHz.
25/50 MHz.
33/66 MHz.
40/80 MHz.
Technology: CMOS.
Cyrix M7 CPU.
ID: DH = 0x00 (family ID), DL = 0x07 (model ID).
DIR0 register: 0x1B.
2.36.11 Cyrix FasCache Cx486DX2-V33 CPU
Low voltage (3.3V) version of the Cyrix FasCache Cx486DX2 CPU.
33/66 MHz.
40/80 MHz.
Technology: CMOS.
ID: DH = 0x00 (family ID), DL = 0x07 (model ID).
DIR0 register: 0x1B.
2.36.12 Cyrix FasCache Cx486DX2-V CPU
Low voltage (4 V) version of the Cyrix FasCache Cx486DX2 CPU.
8 kbyte cache: write-back.
33/66 MHz (announced: fourth quarter 1994).
40/80 MHz (announced: fourth quarter 1994).
Technology: IBM 0.65 micron CMOS.
ID: DH = 0x04 (family ID), DL = 0x80 (model ID, revision).
DIR0 register: 0x1B.
2.36.13 Cyrix FasCache Cx486DX4 CPU
Clock tripled Cyrix FasCache Cx486DX CPU.
Intel i80486DX4 P24C CPU pin compatible.
3 V core, 5 V tolerant I/O.
Dual SMM support: Cyrix SMM / SL compatible SMM.
8 kbyte cache: write-back.
Cyrix FasCache Cx486DX4-GP CPU:
core/bus speed ratio: 3,
DIR0 register: 0x1F,
package: Cyrix FasCache Cx486DX2 CPU pin compatible:
168 pin PGA (Pin Grid Array),
208 pin QFP (Quad Flat Package).
Cyrix FasCache Cx486DX4-GP4 CPU and Cyrix FasCache Cx486DX4-QP:
pin selectable core/bus speed ratio,
not Cyrix FasCache Cx486DX2 CPU pin compatible,
DIR0 register: 0x1B (CLOCKMUL = 0), 0x1F (CLOCKMUL = 1).
25/75 MHz.
33/100 MHz.
September 1995.
Technology: CMOS.
Cyrix M9 CPU.
2.36.14 Cyrix 5x86 CPU
Cyrix 586 CPU with Intel i80486DX4 P24D CPU bus interface.
64 bit internal data bus, 32 bit external data bus.
Clock: 2x, 3x.
16 kbyte unified cache: write-back/write-through, 4-way set-associative,
4 sets of 256 lines, 16 bytes per line.
Superpipelined superscalar: data forwarding, branch prediction,
BTB (Branch Target Buffer),
decoupled load/store unit.
MMU (Memory Management Unit): 32-entry TLB (Translation Look-aside buffer).
SMM (System Management Mode): stop-clock, FPU auto-idle, hardware suspend,
static core.
33/100 or 50/100 MHz: 3.5 W.
40/120 MHz.
3.45 V core, 5 V tolerant I/O.
Package: 168 pin PGA (Pin Grid Array),
208 pin QFP (Quad Flat Package).
Technology: 0.65 micron CMOS (IBM).
2.0E6 transistors.
Die size: 144 mm2.
Cyrix M1sc CPU.
2.37 Texas Instruments TI486 CPU
2.37.1 Texas Instruments TI486SXL-GA CPU (Potomac)
Intel i80486SX CPU instruction/pin compatible.
8 kbyte cache: write-through, 2-way set-associative, 1024 sets,
4 bytes per line.
40 MHz: february 1994.
Package: ceramic PGA (Pin Grid Array).
Technology: CMOS.
ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).
DIR0 register: 0xFE.
2.37.2 Texas Instruments TI486SXL-V-GA CPU (Potomac)
Low power (3.3 V) version of the Texas Instruments TI486SXL-GA CPU.
33 MHz: february 1994.
Technology: CMOS.
ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).
DIR0 register: 0xFE.
2.37.3 Texas Instruments TI486SXL2-GA CPU (Potomac)
Clock doubled version of the Texas Instruments TI486SXL-GA CPU.
20/40 MHz: february 1994.
25/50 MHz: february 1994.
Technology: CMOS.
ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).
DIR0 register: 0xFE.
2.37.4 Texas Instruments TI486SXL2-V-GA CPU (Potomac)
Clock doubled, low power (3.3 V) version of the
Texas Instruments TI486SXL-GA CPU.
20/40 MHz: february 1994.
Technology: CMOS.
ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).
DIR0 register: 0xFE.
2.37.5 Texas Instruments TI486DX2 CPU
Cyrix core.
Intel and Cyrix pin compatible.
33/66 MHz.
40/80 MHz.
2.37.6 Texas Instruments TI486DX4 CPU
Cyrix FasCache Cx486DX4 CPU with Texas Instruments TI486DX2 CPU pin layout.
33/100 MHz (announced December 1995).
2.38 SGS-Thomson ST486 CPU
2.38.1 SGS-Thomson ST486DX2 CPU
Cyrix FasCache Cx486DX2 CPU.
33/66 MHz.
2.39 UMC 486 CPU
The UMC 486 CPU does violate some of Intel's patents and will therefore not be
sold in the USA.
SMM (System Management Mode).
CPUID: "UMC UMC UMC".
Some 3.3 V U5 CPUs are sold as 3 V parts.
2.39.1 UMC U5S CPU
Intel i80486SX CPU instruction/pin compatible, no FPU (Floating Point Unit).
8 kbyte cache.
4 deep write buffer.
25 MHz: August 1994.
33 MHz: 2.25 W, August 1994.
40 MHz: August 1994.
Manufacturing: 0.6 micron CMOS.
ID: step level A: DH = 0x04 (family ID), DL = 0x23 (model ID, revision).
CPUID: family = 0x4, model = 0x2.
2.39.2 UMC U5SD CPU
Intel i80486DX CPU pin compatible UMC U5S CPU.
25 MHz: August 1994.
33 MHz: 2.25 W, August 1994.
40 MHz: August 1994.
Manufacturing: 0.6 micron CMOS.
ID: DH = 0x04 (family ID), DL = 0x1X (model ID, revision).
CPUID: family = 0x4, model = 0x1.
2.39.3 UMC U5SF CPU
UMC U5S CPU with 208 pin QFP (Quad Flat Package) package.
33 MHz (UMC U5SF-SUPER33 CPU).
2.39.4 UMC U5SLV CPU
3.3 V version of the UMC U5S CPU.
25 MHz (UMC U5SLV-SUPER25 CPU).
33 MHz (UMC U5SLV-SUPER33 CPU): 0.76 W, August 1994.
Manufacturing: 0.6 micron CMOS.
Package: 196 pin PGA (Pin Grid Array).
2.39.5 UMC U5FLV CPU
UMC U5SLV CPU with 208 pin LQFP package.
25 MHz (UMC U5FLV-SUPER25 CPU).
33 MHz (UMC U5FLV-SUPER33 CPU).
Label: UMC U5SDLV:
D: 486DX pin compatible PGA (Pin Grid Array),
_: 486SX pin compatible PGA (Pin Grid Array),
F: 486SX pin compatible LQFP,
LV: 3.3 V,
_: 5 V.
2.39.6 UMC U486DX2 CPU
CPUID: 0x43x.
2.39.7 UMC U486SX2 CPU
CPUID: 0x45x.
2.40 Intel OverDrive CPU for Intel i80486 CPU
Many 486 CPU motherboards contain an Intel OverDrive socket in which a more
powerful CPU can be placed (ODP: OverDrive Processor), this being an
Intel i80486DX2 CPU, an Intel i80486DX4 CPU, or an Intel Pentium CPU. It is
possible to remove the old CPU while upgrading. All output pins of the
original CPU are put in 3-state and the power consumption is reduced when the
UP# pin (Upgrade Present) is activated.
An Intel OverDrive CPU will be made available that will fit in the original
PGA (Pin Grid Array) (ODPR: OverDrive Processor Replacement), so motherboards
without an Intel OverDrive socket can be upgraded too.
At this moment it is still unsure if all motherboards with an
Intel OverDrive socket can indeed be upgraded to an Intel Pentium CPU. The
Intel Pentium P24T CPU (ODP), the Intel Pentium CPU upgrade for the blue
238 pin PGA OverDrive socket (Socket 2: 5 V), appears to produce too much heat
for most thermally not compliant systems. It is not even sure if there will
ever be an Intel Pentium CPU upgrade for those motherboards at all (see Intel
OverDrive Processor Upgradability Guide). For the newer motherboards with a
white 237 pin PGA OverDrive socket (Socket 3: 3.3 V, 5 V), that do satisfy the
heat specifications, there will be an Intel Pentium CPU at 3.3 V with a
ventilator on the IC. There are also black 168 pin OverDrive sockets (standard
486 socket) around; these can contain an Intel i80486DX2 ODP CPU or an
Intel i80486DX4 ODP CPU. For the black 169 pin OverDrive sockets (Socket 1:
5 V) of 486SX systems, an Intel i80487SX CPU, an Intel i80486DX2 ODP CPU, or
an Intel i80486DX4 ODP CPU is available. For the 235 pin Overdrive socket
(Socket 6: 3 V) of 486DX4 systems, the same Intel Pentium CPU at 3.3 V that
could be used with Socket 3, can be used here as well.
2.40.1 Intel i80486DX2 CPU for Intel i80486DX CPU (ODPR)
20/40 MHz.
25/50 MHz.
33/66 MHz.
SL Enhanced from June 1993.
No longer available from April 1996.
Package: 168 pin PGA (Pin Grid Array).
Technology: CMOS.
ID: step level A0-A2: DH = 0x04 (family ID), DL = 0x32 (model ID, revision),
step level B1: DH = 0x04 (family ID), DL = 0x33 (model ID, revision),
step level aA0, aA1 (SL Enhanced): DH = 0x04 (family ID), DL = 0x34
(model ID, revision),
step level aB0, aC0 (SL Enhanced): DH = 0x04 (family ID), DL = 0x35
(model ID, revision),
step level A (write-back): DH = 0x04 (family ID), DL = 0x7X (model ID,
revision).
P4T
2.40.2 Intel i80486DX2 CPU for Intel i80486SX CPU (ODPR)
20/40 MHz.
25/50 MHz.
33/66 MHz.
SL Enhanced from June 1993.
No longer available from April 1996.
Package: 168 pin PGA (Pin Grid Array).
Technology: CMOS.
ID: step level A0-A2: DH = 0x04 (family ID), DL = 0x32 (model ID, revision),
step level B1: DH = 0x04 (family ID), DL = 0x33 (model ID, revision),
step level aA0, aA1 (SL Enhanced): DH = 0x04 (family ID), DL = 0x34
(model ID, revision),
step level aB0, aC0 (SL Enhanced): DH = 0x04 (family ID), DL = 0x35
(model ID, revision),
step level A (write-back): DH = 0x04 (family ID), DL = 0x7X (model ID,
revision).
P4T
2.40.3 Intel i80486DX2 CPU for Intel i80486DX CPU (ODP)
16/32 MHz.
20/40 MHz.
25/50 MHz.
33/66 MHz.
SL Enhanced from June 1993.
No longer available from April 1996.
Package: 168 pin PGA (Pin Grid Array).
Technology: CMOS.
ID: step level A0-A2: DH = 0x04 (family ID), DL = 0x32 (model ID, revision),
step level B1: DH = 0x04 (family ID), DL = 0x33 (model ID, revision),
step level aA0, aA1 (SL Enhanced): DH = 0x04 (family ID), DL = 0x34
(model ID, revision),
step level aB0, aC0 (SL Enhanced): DH = 0x04 (family ID), DL = 0x35
(model ID, revision),
step level A (write-back): DH = 0x04 (family ID), DL = 0x7X (model ID,
revision).
2.40.4 Intel i80486DX2 CPU for Intel i80486SX CPU (ODP)
16/32 MHz.
20/40 MHz.
25/50 MHz.
33/66 MHz.
SL Enhanced from June 1993.
No longer available from April 1996.
Package: 169 pin PGA (Pin Grid Array) (487SX).
Technology: CMOS.
P23T.
ID: step level A0-A2: DH = 0x04 (family ID), DL = 0x32 (model ID, revision),
step level B1: DH = 0x04 (family ID), DL = 0x33 (model ID, revision),
step level aA0, aA1 (SL Enhanced): DH = 0x04 (family ID), DL = 0x34
(model ID, revision),
step level aB0, aC0 (SL Enhanced): DH = 0x04 (family ID), DL = 0x35
(model ID, revision),
step level A (write-back): DH = 0x04 (family ID), DL = 0x7X (model ID,
revision).
2.40.5 Intel i80486DX4 CPU for Intel i80486DX CPU, Intel i80486DX2 CPU
(ODP)
3.3 V core (voltage regulator), 5 V I/O.
25/75 MHz max (DX4ODPR75): October 1994, iCOMP 319.
33/100 MHz max (DX4ODPR100): October 1994, iCOMP 435.
No longer available from fall 1996.
Package: 169 pin PGA (Pin Grid Array) (487SX).
ID: step level A: DH = 0x14 (family ID), DL = 0x80 (model ID, revision).
2.40.6 Intel Pentium P24T CPU (ODP)
25 MHz: December 1994.
33 MHz: December 1994.
5 V.
ID: DH = 0x15 (model ID, family ID), DL = 0x31 (revision).
2.40.7 Intel Pentium P24CT CPU (ODP)
32 kbyte cache: 16 kbyte code, 16 kbyte data.
25/63 MHz (PODP5V63): for 25 MHz external bus systems, January 1994,
235 pin PGA (Pin Grid Array), iCOMP 443.
33/83 MHz (PODP5V83): for 33 MHz external bus systems, October 1995,
237/238 pin PGA (Pin Grid Array), iCOMP 581,
no longer available from March 1998.
ID: DH = 0x15 (model ID, family ID), DL = 0x2X (revision).
CPUID: step level B1 (25/63 MHz, SZ953): 1531,
step level B2 (25/63 MHz, SZ990): 1531,
step level C0 (33/83 MHz, SU014): 1532.
2.41 Cyrix Overdrive CPU
DIR0 register: 0xFD.
Compiled, Copyright 1993 - 1998, by A. Offerman. Permission to use, copy, or
distribute this document in a non-commercial way for non-commercial use is
hereby granted, provided that this copyright and permission notice appear in
all copies. All other rights reserved.
This document is provided "as is" without expressed or implied warranty.
The specific products and their respective manufacturers are not to be taken
as endorsements of, nor commercials for, the manufacturer.
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