Партнёры:
Хостинг:
Archive-name: pc-hardware-faq/chiplist/part2
Last-modified: 1998/06/23
Version: 9.9.5
2 CPU (Central Processing Unit)
2.1 Introduction
The central processing unit (CPU) is the "brain" of the computer. Its function
is to execute programs stored in the main memory by fetching their
instructions, examining them, and then executing them one after another.
2.2 Intel i4004 CPU
4 bit data bus.
12 bit address bus (multiplexed).
Separate address space for instructions and data.
1970.
Package: 16 pin ceramic DIP (Dual In-line Package).
Technology: PMOS.
Die size: 24 mm2.
2250 transistors.
First microprocessor ever build.
2.3 Intel i4040 CPU
Intel i4004 CPU with extra features: more instructions,
interrupt support.
4 bit data bus.
12 bit address bus (multiplexed).
Separate address space for instructions and data.
1972.
Package: 24 pin ceramic DIP (Dual In-line Package).
Technology: PMOS.
2.4 Intel i8008 CPU
8 bit data bus.
14 bit address bus (multiplexed).
300 kHz.
April 1972.
Package: 18 pin ceramic DIP (Dual In-line Package).
Technology: PMOS.
3300 transistors.
2.5 Intel i8080/i8080A CPU
Intel i8008 CPU with stack.
8 bit data bus.
16 bit address bus.
Intel i8080 CPU: 2 MHz, PMOS.
Intel i8080A-2 CPU: 2.67 MHz, NMOS.
Intel i8080A-1 CPU: 3.125 MHz, NMOS.
Intel iM8080A: military (-55 - 125 C).
April 1974.
Package: 40 pin CERDIP (CERamic Dual In-line Package).
Intel i8080 CPU: 1973, PMOS, 4500 transistors.
Intel i8080A CPU: 1976, NMOS, 4000 transistors.
2.6 Zilog Z80 CPU
Intel i8080 CPU upward instruction compatible.
Not Intel i8080 CPU pin compatible.
2.5 MHz: NMOS.
4 MHz: NMOS.
6 MHz: NMOS.
8 MHz: NMOS.
10 MHz: CMOS.
1976.
Package: 40 pin CERDIP (CERamic Dual In-line Package).
2.7 Intel i8085A/i8085AH CPU
Intel i8080 CPU upward instruction compatible.
Extra instructions: SIM (Set Interrupt Mask),
RIM (Read Interrupt Mask).
Extra interrupt lines, including NMI (Non-Maskable Interrupt).
8 bit data bus.
16 bit address bus.
Data and address bus are multiplexed.
1976.
Intel i8085A CPU: 3 MHz, NMOS.
Intel iM8085A CPU: military (-55 - 125 C), NMOS.
Intel i8085AH-2 CPU: 5 MHz, HMOS.
Intel i8085AH-1 CPU: 6 MHz, HMOS.
Intel iM8085AH CPU: military (-55 - 125 C), HMOS.
Package: 40 pin CERDIP (CERamic Dual In-line Package).
6200 transistors.
2.8 Intel i8086A/i80C86A CPU, Intel i8088A/i80C88A CPU
1 Mbyte address space, 64 kbyte per segment.
Technology: 2.0 micron.
29E3 transistors.
2.8.1 Intel i8086A/i80C86A CPU
16 bit internal data bus.
16 bit external data bus.
20 bit address bus.
Data and address bus are multiplexed.
May 1978.
Intel i8086A CPU: 4 MHz, NMOS.
Intel i8086AH CPU: 5 MHz, HMOS.
Intel i8086AH-2 CPU: 8 MHz, HMOS.
Intel i8086AH-1 CPU: 10 MHz, HMOS.
Intel i80C86A CPU: 5 MHz, CMOS.
Intel i80C86A-2 CPU: 8 MHz, CMOS.
Intel i80C86A-1 CPU: 10 MHz, CMOS.
12 Mhz: CMOS.
Intel iM80C86A CPU: military (-55 - 125 C).
Used in IBM PC clones, IBM PC/XT clones.
Package: 40 pin CERDIP (CERamic Dual In-line Package).
2.8.2 Intel i8088A/i80C88A CPU
16 bit internal data bus.
8 bit external data bus (can co-operate with all Intel i8085 CPU
periphery chips).
20 bit address bus.
Data and address bus are multiplexed.
February 1979.
Intel i80C88A CPU: 5 MHz, CMOS.
Intel i80C88A-2 CPU: 8 MHz, CMOS.
Intel i80C88A-1 CPU: 10 MHz, CMOS.
12 MHz: CMOS.
Package: 40 pin CERDIP (CERamic Dual In-line Package).
Used in IBM PC (Personal Computer), IBM PC/XT (eXtended Technology).
2.9 AMD Am8086/Am80C86 CPU, AMD Am8088/Am80C88 CPU
2.9.1 AMD Am8086/Am80C86 CPU
Intel i8086 CPU instruction/pin compatible.
AMD Am8086-1 CPU: 10 MHz, HMOS.
AMD Am80C86 CPU: 5 MHz, CMOS.
AMD Am80C86-2 CPU: 8 MHz, CMOS.
AMD Am80C86-1 CPU: 10 MHz, CMOS.
2.9.2 AMD Am8088/Am80C88 CPU
Intel i8088 CPU instruction/pin compatible.
AMD Am8088 CPU: 5 MHz, HMOS.
AMD Am8088-2 CPU: 8 MHz, HMOS.
AMD Am8088-1 CPU: 10 MHz, HMOS.
2.10 Harris HS80C86/883 CPU, Harris HS80C88/883 CPU
2.10.1 Harris HS80C86/883 CPU
Intel i8086 CPU instruction/pin compatible.
Harris HS80C86/883 CPU: 5 MHz, CMOS.
Harris HS80C86-2/883 CPU: 8 MHz, CMOS.
Harris HS80C86-1/883 CPU: 10 MHz, CMOS.
Harris HSMD80C86 CPU: military (-55 - 125 C), CMOS.
2.10.2 Harris HS80C88/883 CPU
Intel i8088 CPU instruction/pin compatible.
Harris HS80C88/883 CPU: 5 MHz, CMOS.
Harris HS80C88-2/883 CPU: 8 MHz, CMOS.
Harris HS80C88-1/883 CPU: 10 MHz, CMOS.
2.11 Siemens SAB8086 CPU, Siemens SAB8088 CPU
2.11.1 Siemens SAB8086 CPU
Intel i8086 CPU instruction/pin compatible.
Siemens SAB8086-2P CPU: 8 MHz.
Siemens SAB8086-1P CPU: 10 MHz.
2.11.2 Siemens SAB8088 CPU
Intel i8088 CPU instruction/pin compatible.
Siemens SAB8088-I-P CPU: 16 MHz.
1986.
2.12 Hitachi H80C88 CPU
Intel i8088 CPU instruction/pin compatible.
1982.
Technology: CMOS.
2.13 Contemporary CPUs
Contemporary 16 bit CPUs to 8086/8088 were Zilog Z8000 CPU,
Fairchild 9445 CPU, Texas Instruments TI9900 CPU and Mil-Std 1750A CPU.
Last is reason DOD (Department Of Defence) contractors were not interested in
8086/8088. Mil-Std 1750A CPU was specified in all contracts of 1979 - 1984
period.
Texas Instruments TI9900 CPU was probably the best of the lot, but
Texas Instruments considered it a closed architecture, so no-one used it.
2.14 Intel i80186/i80C186 CPU, Intel i80188/i80C188 CPU
Intel i8086 CPU / Intel i8088 CPU with extra features:
2 programmable DMA controllers (Direct Memory Access),
3 timers,
PIC (Programmable Interrupt Controller),
integrated clock generator,
Intel i80C186 CPU, Intel i80C188 CPU: DRAM refresh control unit,
Intel i80C186 CPU, Intel i80C188 CPU: power save mode,
extra instructions: all of the Intel i80286 CPU real mode instructions.
The Intel i80C188 CPU has no NPX interface.
2.14.1 Intel i80186/i80C186 CPU
16 bit internal data bus.
16 bit external data bus.
20 bit address bus.
1983.
Intel i80186 CPU: 6 MHz, NMOS.
Intel i80186 CPU: 8 MHz, NMOS.
Intel i80186 CPU: 10 MHz, NMOS.
Intel i80C186 CPU: 10 MHz, CMOS.
Intel i80C186-12 CPU: 12.5 MHz, CMOS.
Intel i80C186-16 CPU: 16 MHz, CMOS.
Intel iM80C186 CPU: military (-55 - 125 C), 10 MHz, CMOS.
Intel iM80C186-12 CPU: military (-55 - 125 C), 12.5 MHz, CMOS.
Intel i80C186XL CPU: low power, static core version of the Intel i80C186 CPU:
Intel i80C186XL CPU: 10 MHz, CMOS,
Intel i80C186XL12 CPU: 12.5 MHz, CMOS,
Intel i80C186XL16 CPU: 16 MHz, CMOS,
Intel i80C186XL20 CPU: 20 MHz, CMOS.
Intel i80C186EA CPU: Intel i80C186 CPU with extra features: idle mode,
power down mode:
Intel i80L186EA8 CPU: 3 V, 8 MHz, CMOS,
Intel i80C186EA12 CPU: 12.5 MHz, CMOS,
Intel i80C186EA16 CPU: 16 MHz, CMOS,
Intel i80C186EA20 CPU: 20 MHz, CMOS.
Intel i80C186EB CPU: low power, static core Intel i80C186 CPU with 2 serial
channels, instead of DMA:
Intel i80C186EB-8 CPU: 8 MHz, CMOS,
Intel i80L186EB-8 CPU: 3 V, 8 MHz, CMOS,
Intel i80C186EB-13 CPU: 13 MHz, CMOS,
Intel i80C186EB-16 CPU: 16 MHz, CMOS.
Intel i80C186EC CPU: Intel i80C186 CPU with extra features: low power,
static core, 2 serial channels, 4 DMA channels, 32 bit watchdog timer:
Intel i80C186EC-13 CPU: 13 MHz, CMOS,
Intel i80C186EC-16 CPU: 16 MHz, CMOS.
2.14.2 Intel i80188/i80C188 CPU
16 bit internal data bus.
8 bit external data bus (can co-operate with all Intel i8085 CPU
periphery chips).
20 bit address bus.
1983.
Intel i80188 CPU: 6 MHz, NMOS.
Intel i80188 CPU: 8 MHz, NMOS.
Intel i80C188 CPU: 10 MHz, CMOS.
Intel i80C188-12 CPU: 12.5 MHz, CMOS.
Intel i80C188-16 CPU: 16 MHz, CMOS.
Intel i80C188XL CPU: low power, static core version of the Intel i80C188 CPU:
Intel i80C188XL CPU: 10 MHz, CMOS,
Intel i80C188XL12 CPU: 12 MHz, CMOS,
Intel i80C188XL16 CPU: 16 MHz, CMOS,
Intel i80C188XL20 CPU: 20 MHz, CMOS.
Intel i80C188EA CPU: Intel i80C188 CPU with extra features: idle mode,
power down mode:
Intel i80L188EA8 CPU: 3 V, 8 MHz, CMOS,
Intel i80C188EA12 CPU: 12.5 MHz, CMOS,
Intel i80C188EA16 CPU: 16 MHz, CMOS,
Intel i80C188EA20 CPU: 20 MHz, CMOS.
Intel i80C188EB CPU: low power, static core Intel i80C188 CPU with 2 serial
channels instead of DMA:
Intel i80C188EB-8 CPU: 8 MHz, CMOS,
Intel i80L188EB-8 CPU: 3 V, 8 MHz, CMOS,
Intel i80C188EB-13 CPU: 13 MHz, CMOS,
Intel i80C188EB-16 CPU: 16 MHz, CMOS.
Intel i80C188EC CPU: Intel i80C188 CPU with extra features: low power,
static core, 2 serial channels, 4 DMA channels, 32 bit watchdog timer:
Intel i80C188EC-13 CPU: 13 MHz, CMOS,
Intel i80C188EC-16 CPU: 16 MHz, CMOS.
2.15 AMD Am80186/Am80188 CPU
Intel i80186/i80188 CPU upward instruction compatible.
2.15.1 AMD Am80L186 CPU
Intel i80186 CPU bus interface.
16 MHz: 3.3 V, 1995.
AMD Embedded Processors E86 Family.
2.15.2 AMD Am80L188 CPU
Intel i80188 CPU bus interface.
16 MHz: 3.3 V, 1995.
AMD Embedded Processors E86 Family.
2.15.3 AMD Am186EM CPU
Intel i80286 CPU style bus interface.
Extra Features: 2 DMA channels,
watchdog timer,
asynchronous & synchronous serial ports,
32 programmable I/O pins.
25 MHz: 1995.
33 MHz: 1995.
40 MHz: 1995.
Package: PQT100.
AMD Embedded Processors E86 Family.
2.16 NEC V30/V20 CPU
Intel i80186 CPU / Intel i80188 CPU upward instruction compatible.
No protected mode.
Extra features: extra instructions: BCD,
Intel i8080 CPU simulation,
fewer CPI (Cycles Per Instruction).
2.16.1 NEC V30 CPU
Intel i8086 CPU pin compatible.
10 MHz.
mPD70116.
NEC V30H CPU: 10, 12, 16 MHz,
packages: 40 pin DIP (Dual In-line Package),
44 pin PLCC (Plastic Leaded Chip Carrier),
52 pin PFP (QFP (Quad Flat Package)),
mPD70116H.
NEC V35 CPU: extra instructions for register bank switches and task switches,
packages: 84 pin PLCC (Plastic Leaded Chip Carrier),
94 pin QFP (Quad Flat Package),
mPD70330, mPD70332.
NEC V35 Plus CPU: NEC V35 CPU with integrated peripherals: PIC, DMA, ports,
serial, timer,
256 bytes RAM,
8 kbyte ROM,
mPD70335.
NEC V35 Software Guard CPU: NEC V35 CPU with 8086 emulation mode and security
mode,
mPD70337.
NEC V50 CPU: undefined opcode triggers INT6,
same speeds,
packages: 68 pin PGA (Pin Grid Array),
68 pin PLCC (Plastic Leaded Chip Carrier),
80 pin PFP (QFP (Quad Flat Package)),
mPD70216.
NEC V50H CPU: 10, 12, 16 MHz,
packages: 68 pin PGA (Pin Grid Array),
80 pin PFP (QFP (Quad Flat Package)),
mPD70216H.
NEC V55 CPU: NEC V50 CPU,
speeds up to 16 MHz.
2.16.2 NEC V20 CPU
Intel i8088 CPU pin compatible.
8 MHz.
10 MHz.
mPD70108.
Also made by Sony under license from NEC.
NEC V20H CPU: 10, 12, 16 MHz,
packages: 40 pin DIP (Dual In-line Package),
44 pin PLCC (Plastic Leaded Chip Carrier),
52 pin PFP (QFP (Quad Flat Package)),
mPD70108H.
NEC V25 CPU: extra instructions for register bank switches and task switches,
packages: 84 pin PLCC (Plastic Leaded Chip Carrier),
94 pin QFP (Quad Flat Package),
mPD70320, mPD70322.
NEC V25 Plus CPU: NEC V25 CPU with integrated peripherals: PIC, DMA, ports,
serial, timer,
256 bytes RAM,
8 kbyte ROM,
mPD70325.
NEC V25 Software Guard CPU: NEC V25 CPU with 8086 emulation mode and security
mode,
mPD70327.
NEC V40 CPU: undefined opcode triggers INT6,
same speeds,
packages: 68 pin PGA (Pin Grid Array),
68 pin PLCC (Plastic Leaded Chip Carrier),
80 pin PFP (QFP (Quad Flat Package)),
mPD70208.
NEC V40H CPU: 10, 12, 16 MHz,
packages: 68 pin PGA (Pin Grid Array),
80 pin PFP (QFP (Quad Flat Package)),
mPD70208H.
NEC V45 CPU: NEC V40 CPU,
speeds up to 16 MHz.
2.17 Siemens SAB80186 CPU, Siemens SAB80188 CPU
2.17.1 Siemens SAB80186 CPU
Intel i80186 CPU instruction/pin compatible.
Siemens SAB80186-N CPU: 8 MHz.
Siemens SAB80186-1 CPU: 10 MHz.
Siemens SAB80186-16 CPU: 16 MHz.
2.17.2 Siemens SAB80188 CPU
Intel i80188 CPU instruction/pin compatible.
Siemens SAB80188-N CPU: 8 MHz.
Siemens SAB80188-1N CPU: 10 MHz.
2.18 Intel i80886 CPU
2.19 Intel i80286 CPU
Real mode: Intel i8086/i8088 CPU mode.
Protected mode: 16 MByte address space, 64 kbyte per segment,
1 Gbyte virtual memory.
16 bit data bus.
24 bit address bus.
1982.
6 MHz.
8 MHz: PLCC (Plastic Leaded Chip Carrier).
10 MHz: PLCC (Plastic Leaded Chip Carrier).
12 MHz: PLCC (Plastic Leaded Chip Carrier).
16 MHz: PLCC (Plastic Leaded Chip Carrier).
20 MHz.
Package: 68 pin CERDIP (CERamic Dual In-line Package).
Technology: HMOS.
134E3 transistors.
Used in IBM PC/AT (Advanced Technology).
2.20 AMD Am80286/Am80C286 CPU
Intel i80286 CPU instruction/pin compatible.
AMD Am80286 CPU: 8 MHz, HMOS.
AMD Am80286 CPU: 10 MHz, HMOS.
AMD Am80286 CPU: 12 MHz, HMOS.
AMD Am80286 CPU: 16 MHz, HMOS.
AMD Am80C286 CPU: 10 MHz, CMOS.
AMD Am80C286 CPU: 12 MHz, CMOS.
AMD Am80C286 CPU: 16 MHz, CMOS.
AMD Am80C286 CPU: 20 MHz, CMOS.
AMD Am80EC286 CPU: low power version of the AMD Am80C286 CPU.
2.21 Harris 80C286 CPU
Intel i80286 CPU instruction/pin compatible.
10 MHz.
12.5 MHz.
16 MHz.
20 MHz.
25 MHz.
Technology: CMOS.
2.22 Siemens SAB80286 CPU
Intel i80286 CPU instruction/pin compatible.
Siemens SAB80286 CPU: 8 MHz.
Siemens SAB80286-1-N CPU: 10 MHz.
Siemens SAB80286-12-N CPU: 12 MHz.
Siemens SAB80286-16 CPU: 16 MHz.
2.23 Fujitsu 80286 CPU
2.24 Kruger 80286 CPU
2.25 Intel i80386 CPU
Real mode: Intel i8086/i8088 CPU mode.
Protected mode: 64 Tbyte virtual memory, 4 Gbyte per segment.
Virtual 8086 mode (V86 mode): parallel simulation of more virtual
Intel i8086/i8088 CPUs.
POPAD bug: EAX register is trashed when there is a memory access instruction
directly after the POPAD instruction.
2.25.1 Intel i80386/i80386DX CPU
32 bit internal data bus.
32 bit external data bus (DX: Double-word eXternal).
32 bit address bus.
12 MHz: first 16 MHz CPUs had clock speed troubles and were released as
12 MHz items.
16 MHz: early Intel i80386 CPUs had a bug in the 32 bit MUL instruction (MUL
bug); it is fixed in the double-sigma step level,
no longer available.
20 MHz: no longer available.
25 MHz: iCOMP 49.
33 MHz: 2000 mW, iCOMP 68.
October 1985.
Package: 132 pin PGA (Pin Grid Array).
Technology: 0.8 micron CMOS.
275E3 transistors.
ID: AH = 0x03 (Intel i80386 CPU).
ID: step level A (Intel i80386 CPU): DH = 0x00 (model ID, family ID),
step level B0-B10 (Intel i80386 CPU, CMOS III): DH = 0x03 (model ID,
family ID), DL = 0x03 (revision),
step level D0 (Intel i80386DX CPU, CMOS III): DH = 0x03 (model ID,
family ID), DL = 0x05 (revision),
step level D1-D2 (Intel i80386DX CPU, CMOS IV): DH = 0x03 (model ID,
family ID), DL = 0x08 (revision),
step level Ex, Fx: DH = 0x03 (model ID, family ID), DL = 0x08 (revision).
2.25.2 Intel i80386SX CPU
32 bit internal data bus.
16 bit external data bus (SX: Single-word eXternal).
24 bit address bus.
June 1988.
16 MHz.
20 MHz: iCOMP 32.
25 MHz: iCOMP 39.
33 MHz.
Package: 100 pin QFP (Quad Flat Package).
Technology: 0.8 micron CMOS.
ID: step level A0: DH = 0x23 (model ID, family ID), DL = 0x04 (revision),
step level B: DH = 0x23 (model ID, family ID), DL = 0x05 (revision),
step level C, D, E: DH = 0x23 (model ID, family ID), DL = 0x08 (revision).
2.25.3 Intel i80386SL CPU
Low power version of the Intel i80386SX CPU: SMM (System Management Mode).
Static core.
Extra pins assigned for power management.
Extra features: PI-bus (Peripheral Interface),
cache controller, tag RAM,
MCU (Memory Control Unit),
ISA-bus driver (Industry Standard Architecture).
Intel i80386SX CPU upward pin compatible.
Other package: 196 pin surface mounted QFP (Quad Flat Package)
(KC80386SLB1A, ISA SX621).
October 1990.
16 MHz.
20 MHz.
25 MHz, iCOMP 41.
33 MHz.
Technology: CMOS.
ID: step level A0: DH = 0x43 (model ID, family ID), DL = 0x10 (revision),
step level A1: DH = 0x43 (model ID, family ID), DL = 0x10 (revision),
step level A2: DH = 0x43 (model ID, family ID), DL = 0x10 (revision),
step level A3: DH = 0x43 (model ID, family ID), DL = 0x10 (revision),
step level B0: DH = 0x43 (model ID, family ID), DL = 0x11 (revision),
step level B1: DH = 0x43 (model ID, family ID), DL = 0x11 (revision).
Signature register (0x30E, OMCU): step level A0: 0x4300,
step level A1: 0x4300,
step level A2: 0x4301,
step level A3: 0x4302,
step level B0: 0x4310,
step level B1: 0x4311.
2.25.4 Intel RapidCAD CPU
Intel i80386 CPU with FPU (Floating Point Unit) (same implementation as
Intel i80486DX CPU).
The Intel RapidCAD CPU consists of a set of 2 chips. The Intel RapidCAD-1
(132 pin PGA) contains the Intel i80386 CPU with FPU. The Intel RapidCAD-2
(68 pin PGA) fits in the Intel i80387DX NPX socket and contains a PLA for the
FERR signal generation.
Intel i80386DX CPU / Intel i80387DX NPX pin compatible.
1992.
25 MHz.
33 MHz: 2.6 W typical, 3500 mW max.
800.000 transistors.
Technology: 0.8 micron CHMOS IV.
ID: step level A: DH = 0x03 (family ID), DL = 0x40 (model ID, revision),
step level B: DH = 0x03 (family ID), DL = 0x41 (model ID, revision).
2.25.5 Intel i80376 microprocessor
Embedded version of Intel i80386SX CPU.
Intel i80386SX CPU pin compatible.
Intel i80386 CPU instruction set, 32 bit protected mode only, no real mode, no
V86 mode, no 286 mode.
No MMU (Memory Management Unit).
16 MHz.
20 MHz.
1988.
Package: 100 pin QFP (Quad Flat Package),
88 pin PGA (Pin Grid Array).
ID: step level A0: DH = 0x33 (model ID, family ID), DL = 0x05 (revision),
step level B: DH = 0x33 (model ID, family ID), DL = 0x08 (revision).
2.25.6 Intel i386SX microprocessor
Embedded version of Intel i80386SX CPU.
Static core.
24 bit address bus.
16 MHz: 5 V, 0-16 MHz, 1993.
20 MHz: 5 V, 0-20 MHz, 1993.
25 MHz: 5 V, 0-25 MHz, 1993.
Package: 100 pin PQFP (Plastic Quad Flat Package),
die,
military (-55 - 125 C).
Technology: CMOS.
ID: DH = 0x23 (model ID, family ID), DL = 0x09 (revision).
2.25.7 Intel i386CX microprocessor
Embedded version of Intel i80386SX CPU.
Static core.
SMM (System Management Mode): system & power management: idle mode, powerdown,
powersave.
26 bit address bus.
12 MHz: 3 V, 0-12 MHz, 1993.
20 MHz: 3.3 V, 0-20 MHz, 1993.
25 MHz: 5 V, 0-25 MHz, 1993.
Package: 100 pin PQFP (Plastic Quad Flat Package),
100 pin SQFP (Shrink Quad Flat Package),
die,
military (-55 - 125 C).
Technology: CMOS.
ID: step level A: DH = 0x23 (model ID, family ID), DL = 0x09 (revision).
2.25.8 Intel i386EX microprocessor
Embedded version of Intel i80386SX CPU.
Static core.
SMM (System Management Mode): system & power management: idle mode, powerdown,
powersave.
26 bit address bus.
16 MHz: 3 V, 0-16 MHz, 1994.
20 MHz: 3.3 V, 0-20 MHz, 1994.
25 MHz: 5 V, 0-25 MHz, 1994.
Package: 132 pin PQFP (Plastic Quad Flat Package),
144 pin SQFP (Shrink Quad Flat Package),
die,
military (-55 - 125 C).
Technology: CMOS.
ID: step level A: DH = 0x23 (model ID, family ID), DL = 0x09 (revision).
2.26 AMD Am386 CPU
Intel i80386 CPU instruction compatible.
Same core and microcode as Intel i80386 CPU.
2.26.1 AMD Am386DX CPU
Low power.
Intel i80386DX CPU instruction/pin compatible.
Intel i80386DX IV CPU microcode.
March 1991.
16 MHz: 2-16 MHz.
20 MHz: 2-20 MHz.
25 MHz: 2-25 MHz.
33 MHz: 2-33 Mhz.
40 MHz: 2-40 MHz.
Technology: 0.8 micron CMOS.
ID: step level A: DH = 0x03 (model ID, family ID), DL = 0x05 (revision),
step level B: DH = 0x03 (model ID, family ID), DL = 0x08 (revision).
2.26.2 AMD Am386DXL CPU
Low power version of AMD Am386DX CPU.
Static core.
Intel i80386DX IV CPU microcode.
Intel i80386DX CPU upward pin compatible.
March 1991.
20 MHz.
25 MHz.
33 MHz.
40 MHz.
Technology: CMOS.
ID: step level A: DH = 0x03 (model ID, family ID), DL = 0x05 (revision),
step level B: DH = 0x03 (model ID, family ID), DL = 0x08 (revision).
2.26.3 AMD Am386DXLV CPU
Low power (SMM: System Management Mode), low voltage (3.3 V - 4.5 V) version
of AMD Am386DX CPU.
Static core.
Intel i80386DX CPU upward pin compatible.
October 1991.
25 MHz.
33 MHz.
Technology: CMOS.
2.26.4 AMD Am386SX CPU
Low power.
Extra pins assigned for power management.
Intel i80386SX CPU upward pin compatible.
July 1991.
16 MHz: 2-16 MHz.
20 MHz: 2-20 MHz.
25 MHz: 2-25 MHz, no longer available.
33 MHz: 2-33 MHz.
40 MHz: 2-40 MHz.
Technology: 0.8 micron CMOS.
ID: step level A1: DH = 0x23 (model ID, family ID), DL = 0x05 (revision),
step level B: DH = 0x23 (model ID, family ID), DL = 0x08 (revision).
2.26.5 AMD Am386SXL CPU
Low power version of AMD Am386SX CPU.
Static core.
July 1991.
20 MHz: 0-20 MHz.
25 MHz: 0-25 MHz.
33 MHz: 0-33 MHz.
40 MHz: 0-40 MHz.
Technology: CMOS.
ID: step level A1: DH = 0x23 (model ID, family ID), DL = 0x05 (revision),
step level B: DH = 0x23 (model ID, family ID), DL = 0x08 (revision).
2.26.6 AMD Am386SXLV CPU
Low power (SMM: System Management Mode), low voltage (3.3 V - 4.5 V) version
of AMD Am386SX CPU.
Static core.
October 1991.
20 MHz.
25 MHz.
33 MHz.
Technology: CMOS.
2.26.7 AMD Am386DE CPU
Embedded static version of the AMD Am386DX CPU.
25 MHz: 1995.
33 MHz: 1995.
Package: PQB132.
AMD Embedded Processors E86 Family.
2.26.8 AMD Am386SE CPU
Embedded static version of the AMD Am386SX CPU.
25 MHz: 1995.
33 MHz: 1995.
Package: PQB100.
AMD Embedded Processors E86 Family.
2.26.9 AMD Am386EM CPU
Intel i80386 CPU instruction compatible.
Extra features: 4 DMA channels with flyby and chaining support,
watchdog timer,
asynchronous & synchronous serial ports,
32 programmable I/O pins,
DRAM controller,
96 Mbyte address space,
JTAG support.
25 MHz: 1995.
33 MHz: 1995.
40 MHz: 1995.
Package: PQR132.
AMD Embedded Processors E86 Family.
2.27 IBM 386 CPU
Intel i80386 CPU instruction compatible.
Some instructions are executed faster than when executed by the
Intel i80386 CPU.
2.27.1 IBM 386SLC CPU
Low power.
Extra pins assigned for power management.
8 kbyte cache.
To be enabled via software.
October 1991.
16 MHz.
20 MHz.
25 MHz: 2.5 W.
Intel i80386SX CPU upward pin compatible (100 pin MQFP (Metal Quad Flat
Package)).
Technology: CMOS.
Die size: 161 mm2.
ID: step level A: DH = 0xA3 (model ID, family ID), DL = 0xXX (revision).
2.28 Chips & Technologies 386 CPU
Intel i80386 CPU instruction compatible, including undocumented
LOADALL386 instruction.
Own microcode (clean room).
Some instructions are executed faster than when executed by the
Intel i80386 CPU.
2.28.1 Chips & Technologies Super386 38600DX CPU
Co-operation with an appropriate NPX causes communication problems, which
causes the over-all performance to drop below that of an Intel i80386DX CPU
with NPX.
Intel i80386DX CPU pin compatible.
33 MHz.
40 MHz: 1650 mW.
No longer available.
Technology: CMOS.
2.28.2 Chips & Technologies 38605DX CPU
512 byte instruction cache.
32 bit internal data bus.
32 bit external data bus.
32 bit address bus.
Not Intel i80386DX CPU pin compatible.
No longer available.
Package: 144 pin PGA (Pin Grid Array).
Technology: CMOS.
2.28.3 Chips & Technologies 38600SX CPU
Intel i80386SX CPU pin compatible.
Never released.
Technology: CMOS.
2.29 IBM 386/486 hybrid CPU
Intel i80486 CPU instruction compatible, no FPU (Floating Point Unit).
Intel i80386 CPU bus interface.
2.29.1 IBM 486DLC CPU
Intel i80386 CPU core, enhanced by IBM.
16 kbyte cache: 4-way set-associative, write-through.
To be enabled via software (BIOS).
32 bit internal data bus.
32 bit external data bus.
32 bit address bus.
Not Intel i80386DX CPU pin compatible.
Technology: CMOS.
2.29.2 IBM 486DLC2 CPU
Clock doubled version of the IBM 486DLC CPU.
Intel i80386 CPU core, enhanced by IBM.
16 kbyte cache: 4-way set-associative, write-through.
To be enabled via software (BIOS).
Intel i80386DX CPU pin compatible.
November 1993.
33/66 MHz.
Technology: CMOS.
2.29.3 IBM 486SLC CPU
Intel i80386 CPU core, enhanced by IBM.
16 kbyte cache: 4-way set-associative, write-through.
To be enabled via software (BIOS).
32 bit internal data bus.
16 bit external data bus.
24 bit address bus.
Not Intel i80386SX CPU pin compatible.
16 MHz.
20 MHz.
20 MHz: 3.3 V, 1.0 W.
25 MHz.
25 MHz: 3.3 V, 1.3 W.
Technology: CMOS.
ID: step level A: DH = 0xA4 (model ID, family ID), DL = 0xXX (revision).
2.29.4 IBM 486SLC2 CPU
Clock doubled version of the IBM 486SLC CPU.
Low voltage: 3.3 V.
Intel i80386 CPU core, enhanced by IBM.
16 kbyte cache: 4-way set-associative, write-through, 16 byte line size.
To be enabled via software (BIOS).
Intel i80386SX CPU pin compatible (100 pin MQFP (Metal Quad Flat Package)).
December 1992.
16/32 MHz.
20/40 MHz: 1.7 W.
25/50 MHz: 1993, 2.3 W.
33/66 MHz: 1993.
40/80 MHz: 1993.
1.349E6 transistors.
Die size: 69 mm2.
ID: step level Ax: DH = 0xA4 (model ID, family ID), DL = 0x1X (revision),
step level Bx: DH = 0xA4 (model ID, family ID), DL = 0x2X (revision).
2.29.5 IBM 486BLX CPU (Blue Lightning)
Intel i80486 CPU core and microcode, no FPU.
16 kbyte cache: 4-way set-associative, write-through, 16 byte line size.
To be enabled via software (BIOS).
Low power (3.3 V).
Power management: SMM (System Management Mode).
Static core.
15 MHz.
20 Mhz.
25 MHz.
33 MHz.
Intel i80386DX CPU upward pin compatible / AMD Am386DXL/Am386DXLV CPU pin
compatible (132 pin MQFP (Metal Quad Flat Package)).
Technology: 0.8 micron CMOS.
Die size: 82 mm2.
1.4E6 transistors.
2.29.6 IBM 486BLX2 CPU (Blue Lightning)
Clock doubled version of the IBM 486BLX CPU.
15/30 MHz.
20/40 MHz.
25/50 MHz: 1993.
33/66 MHz: 1993.
2.29.7 IBM 486BLX3 CPU (Blue Lightning)
Clock tripled version of the IBM 486BLX CPU.
15/45 MHz.
20/60 MHz.
25/75 MHz: 1993.
33/100 MHz: 1993.
ID: step level A: DH = 0x84 (model ID, family ID), DL = 0xXX (revision).
2.30 Cyrix 386/486 hybrid CPU
Intel i80486 CPU instruction compatible, no FPU (Floating Point Unit).
Own core (clean room): not 100% compatible.
Intel i80386 CPU bus interface.
2.30.1 Cyrix Cx486DLC CPU
First generation 40 MHz CPUs had a bug: using a NPX (Cyrix FasMath EMC87 NPX,
Cyrix FasMath Cx83D87 NPX (until November 1991), IIT IIT-3C87 NPX) caused
crashes. These are caused by synchronisation errors in FSAVE and FSTOR
instructions. Later, improved CPUs have an AB prefix printed in the lower
right corner. The Cyrix FasMath 387+ NPX (European name for
Cyrix FasMath Cx83D87 NPX from November 1991) causes no trouble when
co-operating with a bad Cyrix Cx486DLC CPU.
Static core.
1 kbyte unified cache: write-through,
direct mapped / 2-way set-associative,
maximum of 4 non-cachable areas.
Hit rate: 65% without support of cache by motherboard, because of flush at
DMA,
85% with support of cache by motherboard (Cache Coherency Support).
To be enabled via software (BIOS).
Intel i80386DX CPU upward pin compatible.
June 1992.
25 MHz.
33 MHz.
40 MHz: 2800 mW.
Clock Skewing Correction Circuit.
Contains a fast extra 16x16 bit multiplier.
Extra pins assigned for cache, power and A20 management:
cache management: KEN#,
FLUSH#,
RPLSET#,
RPLVAL#,
power management: SUSP#,
SUSPA#,
A20 management: A20M#.
Technology: CMOS.
DIR0 register: 0x01.
2.30.2 Cyrix Cx486SLC CPU
Static core.
1 kbyte unified cache: write-through / write-back,
direct mapped / 2-way set-associative,
maximum of 4 non-cachable areas.
hit rate: 65% without support of cache by motherboard, because of flush at
DMA,
85% with support of cache by motherboard (Cache Coherency Support).
To be enabled via software (BIOS).
Intel i80386SX CPU upward pin compatible.
20 MHz: March 1992.
25 MHz: May 1992.
33 MHz.
40 MHz.
Clock Skewing Correction Circuit.
Contains a fast extra 16x16 bit multiplier.
Extra pins assigned for cache, power and A20 management:
cache management: KEN#,
FLUSH#,
RPLSET#,
RPLVAL#,
power management: SUSP#,
SUSPA#,
A20 management: A20M#.
Technology: CMOS.
0.6E6 transistors.
Die size: 108 mm2.
ID: step level A: DH = 0x04 (family ID), DL = 0x1X (revision),
DH = 0x04 (family ID), DL = 0x2X (revision).
No DIR0 register.
2.30.3 Cyrix Cx486SLC/e CPU
Low power (SMM: System Management Mode) version of Cyrix Cx486SLC CPU.
Static core.
December 1992.
25 MHz.
33 MHz.
Technology: CMOS.
DIR0 register: 0x00.
2.30.4 Cyrix Cx486SLC/e-V CPU
Low power (SMM: System Management Mode), low voltage (3.3 V) version of
Cyrix Cx486SLC CPU.
Static core.
December 1992.
20 MHz.
25 MHz.
Technology: CMOS.
DIR0 register: 0x00.
2.30.5 Cyrix Cx486DLC / Cx486SLC CPU incompatibilities
Same registers.
Same instruction set.
Differences in execution time of various instructions, average CPI (Cycles
Per Instruction) about equal.
Crashes with: NextStep,
DBOS 1.0 DOS extender of Salford FTN/386,
Fortran compiler.
2.30.6 Cyrix Cx486DLC2 CPU
Clock doubled version of the Cyrix Cx486DLC CPU.
Power Management: SMM (System Management Mode).
Static core.
DIR0 register: 0x03.
2.30.7 Cyrix Cx486SLC2 CPU
Clock doubled version of the Cyrix Cx486SLC CPU
Power Management: SMM (System Management Mode).
Static core.
November 1993.
25/50 MHz.
Technology: CMOS.
DIR0 register: 0x02.
2.30.8 Cyrix Cx486DRx CPU
DIR0 register: 0x05.
2.30.9 Cyrix Cx486SRx CPU
Intel i80486 CPU instruction compatible, no FPU (Floating Point Unit).
The chip is placed over the surface mounted 80386SX CPU. The original CPU is
disabled by using the FLOAT pin. Older 16 MHz 80386SX CPUs can not be
upgraded (Cyrix can supply a compatibility test program).
1 kbyte cache.
DIR0 register: 0x04.
2.30.10 Cyrix Cx486DRx2 CPU
Clock doubled version of the Cyrix Cx486DRx CPU.
Incompatibilities: AT&T / Olivetti 386DX-16 and 386DX-20 systems,
Sun i386 systems,
Memorex 386 systems,
IBM PS/2 Model 70/16 MHz (85 ns memory required),
early Compaq Deskpro 386/16 MHz systems with 287 NPX (NPX
to be removed).
September 1993.
16/32 MHz.
20/40 MHz: heat sink.
25/50 MHz: heat sink.
33/66 MHz.
Technology: CMOS.
DIR0 register: 0x07.
2.30.11 Cyrix Cx486SRx2 CPU
Clock doubled version of the Cyrix Cx486SRx CPU.
December 1993.
16/32 MHz.
20/40 MHz.
25/50 MHz.
Technology: CMOS.
DIR0 register: 0x06.
2.30.12 Cyrix Cx486DRu CPU
Direct Replacement Unit.
In fact a Cyrix Cx486DLC CPU with some additional hardware on a little PCB
that fits in a PGA (Pin Grid Array).
DIR0 register: 0x09.
2.30.13 Cyrix Cx486SRu CPU
DIR0 register: 0x08.
2.30.14 Cyrix Cx486DRu2 CPU
Clock doubled version of the Cyrix Cx486DRu CPU.
16/32 MHz.
20/40 MHz.
25/50 MHz.
DIR0 register: 0x0B.
2.30.15 Cyrix Cx486SRu2 CPU
Clock doubled version of the Cyrix Cx486SRu CPU.
DIR0 register: 0x0A.
2.31 Texas Instruments 386/486 hybrid CPU
2.31.1 Texas Instruments TI486DLC CPU
Cyrix Cx486DLC CPU.
ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).
2.31.2 Texas Instruments TI486SLC CPU
Cyrix Cx486SLC CPU.
ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).
2.31.3 Texas Instruments TI486SXL-S-GA CPU (Potomac)
Intel i80486 CPU instruction compatible, no FPU (Floating point Unit).
Intel i80386DX CPU bus interface.
8 kbyte cache: write-through, 2-way set-associative, 1024 sets,
4 bytes per line.
40 MHz: february 1994.
Package: ceramic PGA (Pin Grid Array).
Technology: CMOS.
ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).
DIR0 register: 0xFE.
2.31.4 Texas Instruments TI486SXL-VS-GA CPU (Potomac)
Low power (3.3 V) version of the Texas Instruments TI486SXL-S-GA CPU.
33 MHz: february 1994.
Technology: CMOS.
ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).
DIR0 register: 0xFE.
2.31.5 Texas Instruments TI486SXL2-S-GA CPU (Potomac)
Clock doubled version of the Texas Instruments TI486SXL-S-GA CPU.
20/40 MHz: february 1994.
25/50 MHz: february 1994.
Technology: CMOS.
ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).
DIR0 register: 0xFE.
2.31.6 Texas Instruments TI486SXL2-VS-GA CPU (Potomac)
Clock doubled, low power (3.3 V) version of the
Texas Instruments TI486SXL-S-GA CPU.
20/40 MHz: february 1994.
Technology: CMOS.
ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).
DIR0 register: 0xFE.
2.31.7 Texas Instruments TI486SXLC-PAF CPU (Potomac)
Intel i80486 CPU instruction compatible, no FPU (Floating Point Unit).
Intel i80386SX CPU bus interface.
8 kbyte cache: write-through, 2-way set-associative, 1024 sets,
4 bytes per line.
33 MHz: february 1994.
Package: QFP (Quad Flat Package).
Technology: CMOS.
ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).
DIR0 register: 0xFE.
2.31.8 Texas Instruments TI486SXLC-V-PAF CPU (Potomac)
Low power (3.3 V) version of the Texas Instruments TI486SXLC-PAF CPU.
25 MHz: february 1994.
33 MHz: february 1994.
Technology: CMOS.
ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).
DIR0 register: 0xFE.
2.31.9 Texas Instruments TI486SXLC2-PAF CPU (Potomac)
Clock doubled version of the Texas Instruments TI486SXLC-PAF CPU.
20/40 MHz: february 1994.
25/50 MHz: february 1994.
Technology: CMOS.
ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).
DIR0 register: 0xFE.
2.31.10 Texas Instruments TI486SXLC2-V-PAF CPU (Potomac)
Clock doubled, low power (3.3 V) version of the
Texas Instruments TI486SXLC-PAF CPU.
20/40 MHz: february 1994.
Technology: CMOS.
ID: step level A: DH = 0x04 (family ID), DL = 0x10 (model ID, revision),
step level B: DH = 0x04 (family ID), DL = 0x11 (model ID, revision).
DIR0 register: 0xFE.
2.31.11 Texas Instruments announcements
Rio Grande series: Potomac series follow-up.
Compiled, Copyright 1993 - 1998, by A. Offerman. Permission to use, copy, or
distribute this document in a non-commercial way for non-commercial use is
hereby granted, provided that this copyright and permission notice appear in
all copies. All other rights reserved.
This document is provided "as is" without expressed or implied warranty.
The specific products and their respective manufacturers are not to be taken
as endorsements of, nor commercials for, the manufacturer.
|
Закладки на сайте Проследить за страницей |
Created 1996-2024 by Maxim Chirkov Добавить, Поддержать, Вебмастеру |